1 General Description
SE042BG is an Active Matrix Electrophoretic Display(AM EPD), with interface and a reference system design. The 4.2”
active area contains 400x300 pixels. The module is a TFT-array driving electrophoretic display, with integrated circuits
including gate buffer, source buffer, MCU interface, timing control logic, oscillator, DC-DC, SRAM, LUT, VCOM. Module
can be used in portable electronic devices, such as Electronic ShelfLabel (ESL) System.
2 Features
◆ 400×300 pixels display
◆ White reflectance above 30%
◆ Contrast ratio above 8:1
◆ Ultra wide viewing angle
◆ Ultra low power consumption
◆ Pure reflective mode
◆ Bi-stable display
◆ Commercial temperature range
◆ Landscape, portrait modes
◆ Ultra Low current deep sleep mode
◆ On chip display RAM
◆ Waveform stored in On-chip OTP
◆ Serial peripheral interface available
◆ On-chip oscillator
◆ On-chip booster and regulator control for generating VCOM, Gate and Source driving voltage
◆ I 2C signal master interface to read external temperature sensor
3 Application
Electronic ShelfLabel System
| No | Name | I/O | Deseription | Remark |
| 1 | NC | | Do not connect with other NCpins | |
| 2 | GDR | 0 | N-Channel MOSFET Gate Drive Contro | |
| 3 | RESE | I | Current Sense Input for the Control Loop | |
| 4 | NC | | Do not connect with other NCpins | |
| 5 | VDHR | C | Positive Source driving voltage 1 | |
| 6 | TSCL | 0 | ²C Interface to digital temperature sensor Clockpin | |
| 7 | TSDA | I/O | IC Interface to digital temperature sersorData pin | |
| 8 | BS | I | Bus Interface selection pin | Note 5-4 |
| 9 | BUSYN | 0 | Busy state output pin | Note 5-3 |
| 10 | RSTN | I | Reset signal input.Active Low. | |
| 1 | DC | I | Data /Command control pin | Note 5-2 |
| 12 | CSB | I | Chip select inputpin | Note 5-1 |
| 13 | SCL | I | Serial Clockpin(SPD) | |
| 14 | SDA | I | Serial Data pin(SPD | |
| 15 | VDD | P | Power Supply for interface logic pins | |
| 16 | VDD | P | Power Supply for the chip | |
| 17 | VSS | P | Ground | |
| 18 | VDDD | C | Core logic power pin
VDDD can be regulated internally fromVDD.A capac itor
should be connected between VDDD and VSS under all
circumstances | |
| 19 | VPP | P | Power Supply for OTPProgramming | |
| 20 | VSH | C | Positive Source driving voltage | |
| 21 | VGH | C | Positive Gate driving voltage | |
| 22 | VSL | C | Negative Source driving voltage | |
| 23 | VGL | C | Negative Gate driving voltage | |
| 24 | VCOM | C | VCOM drivingvoltage | |
